With the continued miniaturization of integrated circuit (IC) devices, the present trend is to produce integrated circuits having shallower junction depths, thinner gate oxides, lightly-doped drain (LDD) structures, shallow trench isolation (STI) structures, and self-aligned silicide (salicide) processes, all of which are used in advanced sub-quarter-micron complementary metal oxide semiconductor (CMOS) technologies. All of these processes cause the related CMOS IC products to become more susceptible to damage due to electrostatic discharge (ESD) events. ESD is a serious problem confronting circuit designers, because electrostatic voltages can build up from a variety of environmental sources and can reach high voltage values. During discharge, high transient currents can damage equipment by generating high temperatures that can melt circuit components. Therefore, ESD protection circuits are built onto the chip to protect the devices and circuits on the IC from ESD damage.
An ESD protection circuit is typically added to integrated circuits (ICs) at bond pads. The pads are the connections to outside circuits, for electric power supplies, electric grounds, and electronic signals. An ESD protection circuit has two states: normal operation mode and ESD mode. When an IC is in the normal operation mode, the ESD protection circuit appears invisible to the IC by blocking current through itself. In the ESD mode, the ESD protection circuit provides an electrical path to a safe terminal, typically a power supply pin or ground pin, and causes the electrostatic current (called a “strike”) to bypass the susceptible semiconductor devices formed within the IC.
ESD events typically happen between an input, input/output or output pad and another terminal, either VSS (ground) or VDD (positive power supply). Four modes of ESD stress are commonly described. A positive voltage from a pad to VSS is referred to as a PS strike, a positive voltage from a pad to VDD is referred to as a PD strike, a negative voltage from a pad to VSS is referred to as an NS strike, and a negative voltage from a pad to VDD is referred to as a ND strike.